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SSTU32866 1.8 v 25-bit 1:1 or 14-bit 1:2 con?gurable registered buffer with parity for ddr2 rdimm applications rev. 01 09 july 2004 objective data 1. description the SSTU32866 is a 1.8 v con?gurable register speci?cally designed for use on ddr2 memory modules requiring a parity checking function. it is de?ned in accordance with the jedec jesd82-7 standard for the sstu32864 registered buffer, while adding the parity checking function in a compatible pinout. the jedec standard for SSTU32866 is pending publication. the register is con?gurable (using con?guration pins c0 and c1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter con?guration can be designated as register a or register b on the dimm. the SSTU32866 accepts a parity bit from the memory controller on its parity bit (par_in) input, compares it with the data received on the dimm-independent d-inputs and indicates whether a parity error has occurred on its open-drain qerr pin (active-low). the convention is even parity, i.e., valid parity is de?ned as an even number of ones across the dimm-independent data inputs combined with the parity input bit. the SSTU32866 is packaged in a 96-ball, 6 16 grid, 0.8 mm ball pitch lfbga package (13.5 mm by 5.5 mm). 2. features n con?gurable register supporting ddr2 registered dimm applications n con?gurable to 25-bit 1:1 mode or 14-bit 1:2 mode n controlled output impedance drivers enable optimal signal integrity and speed n exceeds jesd82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) n supports up to 450 mhz clock frequency of operation n optimized pinout for high-density ddr2 module design n chip-selects minimize power consumption by gating data outputs from changing state n supports sstl_18 data inputs n checks parity on the dimm-independent data inputs n partial parity output and input allows cascading of two SSTU32866s for correct parity error processing n differential clock (ck and ck) inputs n supports lvcmos switching levels on the control and reset inputs n single 1.8 v supply operation n available in 96-ball, 13.5 5.5 mm, 0.8 mm ball pitch lfbga package
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 2 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. applications n ddr2 registered dimms desiring parity checking functionality 4. ordering information 5. pinning information table 1: ordering information t amb =0 cto+70 c. type number package name description solder process version SSTU32866ec/g lfbga96 plastic low pro?le ?ne-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm pb-free (snagcu solder ball compound) sot536-1 SSTU32866ec lfbga96 plastic low pro?le ?ne-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm snpb solder ball compound sot536-1 table 2: ball mapping, 1:1 register (c0 = 0, c1 = 0) 96-ball, 6 16 grid; top view. dnu denotes do not use. nc denotes a no-connect (ball present but not connected to the die). 1 2 3 4 5 6 a dcke ppo v ref v dd qcke dnu b d2 d15 gnd gnd q2 q15 c d3 d16 v dd v dd q3 q16 d dodt qerr gnd gnd qodt dnu e d5 d17 v dd v dd q5 q17 f d6 d18 gnd gnd q6 q18 g par_in reset v dd v dd c1 c0 h ck dcs gnd gnd qcs dnu j ck csr v dd v dd nc nc k d8 d19 gnd gnd q8 q19 l d9 d20 v dd v dd q9 q20 m d10 d21 gnd gnd q10 q21 n d11 d22 v dd v dd q11 q22 p d12 d23 gnd gnd q12 q23 r d13 d24 v dd v dd q13 q24 t d14 d25 v ref v dd q14 q25
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 3 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 3: ball mapping, 1:2 register a (c0 = 0, c1 = 1) 96-ball, 6 16 grid; top view. dnu denotes do not use. nc denotes a no-connect (ball present but not connected to the die). 1 2 3 4 5 6 a dcke ppo v ref v dd qckea qckeb b d2 dnu gnd gnd q2a q2b c d3 dnu v dd v dd q3a q3b d dodt qerr gnd gnd qodta qodtb e d5 nc v dd v dd q5a q5b f d6 nc gnd gnd q6a q6b g par_in reset v dd v dd c1 c0 h ck dcs gnd gnd qcsa qcsb j ck csr v dd v dd nc nc k d8 dnu gnd gnd q8a q8b l d9 dnu v dd v dd q9a q9b m d10 dnu gnd gnd q10a q10b n d11 dnu v dd v dd q11a q11b p d12 dnu gnd gnd q12a q12b r d13 dnu v dd v dd q13a q13b t d14 dnu v ref v dd q14a q14b table 4: ball mapping, 1:2 register b (c0 = 1, c1 = 1) 96-ball, 6 16 grid; top view. dnu denotes do not use. nc denotes a no-connect (ball present but not connected to the die). 1 2 3 4 5 6 a d1 ppo v ref v dd q1a q1b b d2 dnu gnd gnd q2a q2b c d3 dnu v dd v dd q3a q3b d d4 qerr gnd gnd q4a q4b e d5 dnu v dd v dd q5a q5b f d6 dnu gnd gnd q6a q6b g par_in reset v dd v dd c1 c0 h ck dcs gnd gnd qcsa qcsb j ck csr v dd v dd nc nc k d8 dnu gnd gnd q8a q8b l d9 dnu v dd v dd q9a q9b m d10 dnu gnd gnd q10a q10b n dodt dnu v dd v dd qodta qodtb p d12 dnu gnd gnd q12a q12b r d13 dnu v dd v dd q13a q13b t dcke dnu v ref v dd qckea qckeb
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 4 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5.1 pin description [1] data inputs = d2, d3, d5, d6, d8 to d25 when c0 = 0 and c1 = 0. data inputs = d2, d3, d5, d6, d8 to d14 when c0 = 0 and c1 = 1. data inputs = d1 to d6, d8 to d10, d12, d13 when c0 = 1 and c1 = 1. [2] data outputs = q2, q3, q5, q6, q8 to q25 when c0 = 0 and c1 = 0. data outputs = q2, q3, q5, q6, q8 to q14 when c0 = 0 and c1 = 1. data outputs = q1 to q6, q8 to q10, q12, q13 when c0 = 1 and c1 = 1. table 5: pin description signal name type description gnd ground input ground. v dd 1.8 v nominal power supply voltage. v ref 0.9 v nominal input reference voltage. ck differential input positive master clock input. ck differential input negative master clock input. c0, c1 lvcmos inputs con?guration control inputs; register a or register b and 1:1 mode or 1:2 mode select. reset lvcmos input asynchronous reset input. resets registers and disables v ref data and clock. csr, dcs sstl_18 input chip select inputs. disables d1 to d25 [1] outputs switching when both inputs are high. d1 to d25 sstl_18 input data input. clocked in on the crossing of the rising edge od ck and the falling edge of ck. dodt sstl_18 input the outputs of this register bit will not be suspended by the dcs and csr control. dcke sstl_18 input the outputs of this register bit will not be suspended by the dcs and csr control. par_in sstl_18 input parity input. arrives one clock cycle after the corresponding data input. q1 to q25 [2] 1.8 v cmos outputs data outputs that are suspended by the dcs and csr control. ppo 1.8 v cmos output partial parity out. indicates odd parity of inputs d1 to d25 [1] . qcs 1.8 v cmos output data output that will not be suspended by the dcs and csr control. qodt 1.8 v cmos output data output that will not be suspended by the dcs and csr control. qcke 1.8 v cmos output data output that will not be suspended by the dcs and csr control. qerr open-drain output output error bit. generated one clock cycle after the corresponding data output nc no internal connection. dnu do not use. inputs are in standby-equivalent mode and outputs are driven low.
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 5 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. functional description the SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 con?gurable registered buffer with parity, designed for 1.7 v to 1.9 v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control and reset ( reset) inputs are lvcmos. all data outputs are 1.8 v cmos drivers that have been optimized to drive the ddr2 dimm load, and meet sstl_18 speci?cations. the error ( qerr) output is 1.8 v open-drain driver. the SSTU32866 operates from a differential clock (ck and ck). data are registered at the crossing of ck going high, and ck going low. the c0 input controls the pinout con?guration for the 1:2 pinout from a con?guration (when low) to b con?guration (when high). the c1 input controls the pinout con?guration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). the SSTU32866 accepts a parity bit from the memory controller on its parity bit (par_in) input, compares it with the data received on the dimm-independent d-inputs and indicates whether a parity error has occurred on its open-drain qerr pin (active-low). the convention is even parity, i.e., valid parity is de?ned as an even number of ones across the dimm-independent data inputs combined with the parity input bit. when used as a single device, the c0 and c1 inputs are tied low. in this con?guration, parity is checked on the par_in input which arrives one cycle after the input data to which it applies. the partial-parity-out (ppo) and qerr signals are produced three cycles after the corresponding data inputs. when used in pairs, the c0 input of the ?rst register is tied low and the c0 input of the second register is tied high. the c1 input of both registers are tied high. parity, which arrives one cycle after the data input to which it applies, is checked on the par_in input of the ?rst device. the ppo and qerr signals are produced on the second device three clock cycles after the corresponding data inputs. the ppo output of the ?rst register is cascaded to the par_in of the second register. the qerr output of the ?rst register is left ?oating and the valid error information is latched on the qerr output of the second register. if an error occurs and the qerr output is driven low, it stays latched low for two clock cycles or until reset is driven low. the dimm-dependent signals (dcke, dcs, dodt, and csr) are not included in the parity check computation. the device supports low-power standby operation. when reset is low, the differential input receivers are disabled, and undriven (?oating) data, clock and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs are forced low. the lvcmos reset input must always be held at a valid logic high or low level. the device also supports low-power active operation by monitoring both system chip select ( dcs and csr) inputs and will gate the qn and ppo outputs from changing states when both dcs and csr inputs are high. if either dcs or csr input is low, the qn and ppo outputs will function normally. the reset input has priority over the dcs and csr control and when driven low will force the qn and ppo outputs low, and the qerr output high. if the dcs control functionality is not desired, then the
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 6 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. csr input can be hard-wired to ground, in which case, the set-up time requirement for dcs would be the same as for the other d data inputs. to control the low-power mode with dcs only, then the csr input should be pulled up to v dd through a pull-up resistor. to ensure de?ned outputs from the register before a stable clock has been supplied, reset must be held in the low state during power-up. in the ddr2 rdimm application, reset is speci?ed to be completely asynchronous with respect to ck and ck. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the qn outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the SSTU32866 must ensure that the outputs will remain low, thus ensuring no glitches on the output.
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 7 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.1 function table [1] data inputs = d2, d3, d5, d6, d8 to d25 when c0 = 0 and c1 = 0. data inputs = d2, d3, d5, d6, d8 to d14 when c0 = 0 and c1 = 1. data inputs = d1 to d6, d8 to d10, d12, d13 when c0 = 1 and c1 = 1. [2] par_in arrives one clock cycle (c0 = 0), or two clock cycles (c0 = 1), after the data to which it applies. [3] this transition assumes qerr is high at the crossing of ck going high and ck going low. if qerr is low, it stays latched low for two clock cycles or until reset is driven low. table 6: function table (each ?ip-?op) inputs outputs reset dcs csr ck ck dn, dodtn, dcken qn qcs qodt, qcke hl l - llll hl l - hhlh h l l l or h l or h x qo qo qo hl h - llll hl h - hhlh h l h l or h l or h x qo qo qo hh l - llhl hh l - hhhh h h l l or h l or h x qo qo qo hh h - lqohl hh h - hqohh h h h l or h l or h x qo qo qo l x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating l l l table 7: parity and standby function table inputs outputs reset dcs csr ck ck ? of inputs = h (d1 to d25) par_in [1] ppo [2] qerr hl x - even l l h hl x - odd l h l hl x - even h h l hl x - odd h l h hh l - even l l h hh l - odd l h l hh l - even h h l hh l - odd h l h hh h - x x ppoo qerro h x x l or h l or h x x ppoo qerro l x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating l h
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 8 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.2 logic diagram (1) disabled in 1:1 con?guration. fig 1. logic diagram 1:2 register a con?guration with c0 = 0 and c1 = 1 (positive logic). 002aaa649 1d r 1d r 1d r qckea qckeb (1) qodta qodtb (1) qcsa qcsb (1) c1 c1 c1 csr dcs dodt dcke d2 0 1 1d r q2a q2b (1) c1 to 10 other channels (d3, d5, d6, d8Cd14) ck v ref ck reset
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 9 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 2. parity logic diagram for 1:2 register a con?guration (positive logic); c0 = 0, c1 = 1. 002aaa650 d r q2aCq3a, q5aCq6a, q8aCq14a q2bCq3b, q5bCq6b, q8bCq14b clk par_in d2Cd3, d5Cd6, d8Cd14 ck ck reset lps0 (internal node) ce v ref 11 11 d2Cd3, d5Cd6, d8Cd14 parity check c1 0 1 d r clk d r clk ce d r clk 1 0 c0 r clk d r clk lps1 (internal node) 0 1 2-bit counter qerr ppo d2Cd3, d5Cd6, d8Cd14 11 11 11
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 10 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. limiting values [1] stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operatin g conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. [3] this value is limited to 2.5 v maximum. 8. recommended operating conditions table 8: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +2.5 v v i receiver input voltage [2] , [3] - 0.5 +2.5 v v o driver output voltage [2] , [3] - 0.5 v dd + 0.5 v i ik input clamp current v i < 0 or v i >v dd - - 50 ma i ok output clamp current v o < 0 or v o >v dd - 50 ma i o continuous output current 0 < v o < v dd - 50 ma i ccc continuous current through each v dd or gnd pin - 100 ma t stg storage temperature - 65 +150 c esd hbm electrostatic discharge human body model; 1.5 k w ; 100 pf >2 - kv esd mm electrostatic discharge machine model; 0 w ; 200 pf >200 - v table 9: recommended operating conditions symbol parameter conditions min nom max unit v dd supply voltage 1.7 - 1.9 v v ref reference voltage 0.49 v dd 0.50 v dd 0.51 v dd v v tt termination voltage v ref - 40 mv v ref v ref +40mv v v i input voltage 0 - v dd v v ih ac high-level input voltage data, csr, and par_in inputs v ref + 250 mv - - v v il ac low-level input voltage data, csr, and par_in inputs --v ref - 250 mv v v ih dc high-level input voltage data, csr, and par_in inputs v ref + 125 mv - - v v il dc low-level input voltage data, csr, and par_in inputs --v ref - 125 mv v v ih high-level input voltage reset, cn 0.65 v dd -- v v il low-level input voltage reset, cn - - 0.35 v dd v v icr common mode input voltage range ck, ck 0.675 - 1.125 v v id differential input voltage ck, ck 600 - - mv
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 11 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the reset and cn inputs of the device must be held at valid levels (not ?oating) to ensure proper device operation. the differentia l inputs must not be ?oating, unless reset is low. 9. static characteristics i oh high-level output current - - - 8ma i ol low-level output current - - 8 ma t amb operating ambient temperature in free air 0 - +70 c table 9: recommended operating conditions continued symbol parameter conditions min nom max unit table 10: dc electrical characteristics over recommended operating conditions, unless otherwise noted. symbol parameter conditions min typ max unit v oh high-level output voltage i oh = - 6 ma; v dd = 1.7 v 1.2 - - v v ol low-level output voltage i ol = 6 ma; v dd = 1.7 v - - 0.5 v i i input current all inputs; v i =v dd or gnd; v dd = 1.9 v -- 5 m a i dd static standby current reset = gnd; i o = 0 ma; v dd = 1.9 v - - 100 m a static operating current reset = v dd ; i o = 0 ma; v dd = 1.9 v; v i =v ih(ac) or v il(ac) - - 40 ma i ddd dynamic operating current, clock only reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. i o = 0 ma; v dd = 1.8 v -16- m a / mhz dynamic operating current, per each data input, 1:1 mode reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. i o = 0 ma; v dd = 1.8 v -11- m a / mhz dynamic operating current, per each data input, 1:2 mode reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. i o = 0 ma; v dd = 1.8 v -19- m a / mhz c i input capacitance, data and csr inputs v i =v ref 250 mv; v dd = 1.8 v 2.5 - 3.5 pf input capacitance, ck and ck inputs v icr = 0.9 v; v i(p-p) = 600 mv; v dd = 1.8 v 2-3pf input capacitance, reset input v i =v dd or gnd; v dd = 1.8 v 3 - 4 pf
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 12 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. dynamic characteristics [1] this parameter is not necessarily production tested. [2] v ref must be held at a valid input voltage level and data inputs must be held low for a minimum time of t act (max) after reset is taken high. [3] v ref , data and clock inputs must be held at valid levels (not ?oating) a minimum time of t inact (max) after reset is taken low. [1] includes 350 ps of test-load transmission line delay. [2] this parameter is not necessarily production tested. table 11: timing requirements over recommended operating conditions, unless otherwise noted. see figure 2 . symbol parameter conditions min typ max unit f clock clock frequency - - 450 mhz t w pulse duration, ck, ck high or low 1- - ns t act differential inputs active time [1] , [2] --10ns t inact differential inputs inactive time [1] , [3] --15ns t su set-up time dcs before ck - , ck , csr high; csr before ck - , ck , dcs high 0.7 - - ns dcs before ck - , ck , csr low 0.5 - - ns dodt, dcke and data before ck - , ck 0.5 - - ns par_in before ck - , ck 0.5 - - ns t h hold time dcs, dodt, dcke and data after ck - , ck 0.5 - - ns par_in after ck - , ck 0.5 - - ns table 12: switching characteristics over recommended operating conditions, unless otherwise noted. see section 11.1 . symbol parameter conditions min typ max unit f max maximum input clock frequency 450 - - mhz t pdm propagation delay, single bit switching from ck - and ck to qn [1] 1.41 - 1.8 ns t pd propagation delay from ck - and ck to ppo 0.5 - 1.8 ns t lh low-to-high propagation delay from ck - and ck to qerr 1.2 - 3 ns t hl high-to-low propagation delay from ck - and ck to qerr 1 - 2.4 ns t pdmss propagation delay, simultaneous switching from ck - and ck to qn [1] , [2] - - 2.0 ns t phl high-to-low propagation delay from reset to qn --3ns from reset to ppo --3ns t plh low-to-high propagation delay from reset to qerr - --3ns
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 13 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate). 10.1 timing diagrams table 13: data output edge rates over recommended operating conditions, unless otherwise noted. see section 11.2 . symbol parameter conditions min typ max unit dv/dt_r rising edge slew rate from 20% to 80% 1 - 4 v/ns dv/dt_f falling edge slew rate from 80% to 20% 1 - 4 v/ns dv/dt_ d [1] absolute difference between dv/dt_r and dv/dt_f from 20% or 80% to 80% or 20% - - 1 v/ns fig 3. timing diagram for SSTU32866 used as a single device; c0 = 0, c1 = 0. reset dcs csr ck ck d1Cd14 q1Cq14 par_in ppo qerr (not used) t su t h n n + 1 n + 2 n + 3 n + 4 t pd ck to q t su t h t pd ck to ppo t pd ck to qerr 002aaa656 t pd ck to qerr
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 14 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 4. timing diagram for the ?rst SSTU32866 (1:2 register a con?guration) device used in pair; c0 = 0, c1 = 1. reset dcs csr ck ck d1Cd14 q1Cq14 par_in ppo qerr (not used) t su t h n n + 1 n + 2 n + 3 n + 4 t pd ck to q t su t h t pd ck to ppo t pd ck to qerr 002aaa656 t pd ck to qerr
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 15 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) par_in is driven from ppo of the ?rst SSTU32866 device. fig 5. timing diagram for the second SSTU32866 (1:2 register b con?guration) device used in pair; c0=1,c1=1. reset dcs csr ck ck d1Cd14 q1Cq14 par_in (1) ppo (not used) qerr t su t h n n + 1 n + 2 n + 3 n + 4 t pd ck to q t su t h t pd ck to ppo t pd ck to qerr 002aaa657 t pd ck to qerr
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 16 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. test information 11.1 parameter measurement information for data output load circuit v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20%, unless otherwise speci?ed. the outputs are measured one at a time with one transition per measurement. (1) c l includes probe and jig capacitance. fig 6. load circuit, data output measurements. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. fig 7. voltage and current waveforms; inputs active and inactive times. v id = 600 mv v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 8. voltage waveforms; pulse duration. r l = 100 w r l = 1000 w v dd t l = 50 w ck inputs ck ck out dut test point 002aaa371 test point t l = 350 ps, 50 w r l = 1000 w c l = 30 pf see note (1) lvcmos reset 10% i dd (see note) t inact v dd v dd /2 t act 90% 0 v 002aaa372 v dd /2 v icr v icr v ih v il input t w v id 002aaa373
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 17 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. v id = 600 mv v ref =v dd /2 v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 9. voltage waveforms; set-up and hold times. t plh and t phl are the same as t pd . fig 10. voltage waveforms; propagation delay times. t plh and t phl are the same as t pd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 11. voltage waveforms; propagation delay times. t su v ih v il v id t h ck ck input v ref v ref v icr 002aaa374 v oh v ol output t plh 002aaa375 v tt v icr v icr t phl ck ck v i(p-p) t phl 002aaa376 lvcmos reset input output v tt v dd /2 v ih v il v oh v ol
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 18 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.2 data output slew rate measurement information v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20%, unless otherwise speci?ed. (1) c l includes probe and jig capacitance. fig 12. load circuit, high-to-low slew measurement. fig 13. voltage waveforms, high-to-low slew rate measurement. (1) c l includes probe and jig capacitance. fig 14. load circuit, low-to-high slew measurement. fig 15. voltage waveforms, low-to-high slew rate measurement. c l = 10 pf see note (1) v dd out dut test point r l = 50 w 002aaa377 v oh v ol output 80% 20% dv_f dt_f 002aaa378 c l = 10 pf see note (1) out dut test point r l = 50 w 002aaa379 v oh v ol 80% 20% dv_r dt_r output 002aaa380
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 19 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.3 error output load circuit and voltage measurement information v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20%, unless otherwise speci?ed. (1) c l includes probe and jig capacitance. fig 16. load circuit, error output measurements. fig 17. voltage waveforms, open-drain output low-to-high transition time with respect to reset input. fig 18. voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs. c l = 10 pf see note (1) v dd out dut test point r l = 1 k w 002aaa500 v cc /2 t plh v cc 0 v 0.15 v v oh 0 v output waveform 2 lvcmos reset input 002aaa501 v icr t hl v cc /2 v cc v ol timing inputs output waveform 1 v i(p-p) v icr 002aaa502
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 20 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.4 partial parity out load circuit and voltage measurement information v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20%, unless otherwise speci?ed. fig 19. voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs. v icr t lh v oh 0 v timing inputs output waveform 2 v i(pp) v icr 0.15 v 002aaa503 (1) c l includes probe and jig capacitance. fig 20. partial parity out load circuit. v tt =v dd /2 t plh and t phl are the same as t pd . v i(p-p) = 600 mv fig 21. partial parity out voltage waveforms; propagation delay times with respect to clock inputs. c l = 5 pf see note (1) out dut test point r l = 1 k w 002aaa654 v oh v ol output t plh 002aaa375 v tt v icr v icr t phl ck ck v i(p-p)
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 21 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. v tt =v dd /2 t plh and t phl are the same as t pd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il =v dd for lvcmos inputs. fig 22. partial parity out voltage waveforms; propagation delay times with respect to reset input. t phl 002aaa376 lvcmos reset input output v tt v dd /2 v ih v il v oh v ol
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 22 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. package outline fig 23. lfbga96 package outline (sot536-1). 0.8 a 1 b a 2 unit d y e references outline version european projection issue date 00-03-04 03-02-05 iec jedec jeita mm 1.5 0.41 0.31 1.2 0.9 5.6 5.4 y 1 13.6 13.4 0.51 0.41 0.1 0.2 e 1 4 e 2 12 dimensions (mm are the original dimensions) sot536-1 e 0.15 v 0.1 w 0 5 10 mm scale sot536-1 lfbga96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm a max. a a 2 a 1 detail x e e x d e a b c d e f h g j k l m p n r t 246 135 b a e 2 e 1 ball a1 index area ball a1 index area y y 1 c b c a c c b ? v m ? w m 1/2 e 1/2 e
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 23 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 24 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 14: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity objective data rev. 01 09 july 2004 25 of 27 9397 750 12145 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 14. revision history table 15: revision history rev date cpcn description 01 20040709 - objective data (9397 750 12145).
9397 750 12145 philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data rev. 01 09 july 2004 26 of 27 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 09 july 2004 document order number: 9397 750 12145 contents philips semiconductors SSTU32866 1.8 v ddr2 con?gurable registered buffer with parity 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 8 recommended operating conditions. . . . . . . 10 9 static characteristics. . . . . . . . . . . . . . . . . . . . 11 10 dynamic characteristics . . . . . . . . . . . . . . . . . 12 10.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 13 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 16 11.1 parameter measurement information for data output load circuit. . . . . . . . . . . . . . . . . . 16 11.2 data output slew rate measurement information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3 error output load circuit and voltage measurement information . . . . . . . . . . . . . . . 19 11.4 partial parity out load circuit and voltage measurement information . . . . . . . . . 20 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 24 13.5 package related soldering information . . . . . . 24 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 26 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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